The present invention relates to a synchronous random access memory device, and more particularly to a synchronous random access memory device having an input/output scheme capable of operating in a burst mode.
Conventional random access memory devices perform read/write operations in response to an internal clock signal generated within the memory device. As is generally known, it is difficult to adapt conventional random access memory devices to operate at a speed compatible with overall system speed. This difficulty is primarily due to the complicated timing considerations of the memory device and limitations to the internal clock speed. Previous attempts to address this problem have resulted in various techniques for implementing a "synchronous" random access memory device. A synchronous random access memory device generally receives a system clock synchronous to the processing speed of the overall system and the circuitry internal to the memory device is operated in such a manner as to accomplish read/write operations in synchronism with the system clock.
In one conventional approach to the foregoing problem, the synchronous random access memory device operates in a burst mode wherein a counter automatically generates the next addresses upon receipt of an external address. The burst mode operation, thus, requires a burst counter and a burst address decoder on the same chip as the memory device. Burst mode operation is otherwise defined by the system user. Unfortunately, operating speeds for "burst mode" memory devices are not as high as desired because operating speed is degraded by transition of the output data through the burst counter and the burst address decoder.
FIG. 1 is a block diagram showing a counter and other related circuits in a conventional synchronous random access memory device. Referring to FIG. 1, each signal can be referenced in the 1993 memory data book published by Samsung Electronics Co., Ltd., which is incorporated by reference herein. In FIG. 1, counter 300 serves as the conventional burst counter described above. In synchronism with the externally provided system clock signal XK, and when signal XK changes from logical "high" to "low", a counter control circuit 600 receives signal XCONTROL. While signal XCONTROL is low, an externally applied address signal is received. While XCONTROL is high, the address signal is automatically determined according to a counting method preceding burst mode operation. Counter 300 is connected to the lines PDO1, PDO2, . . . PDn of main decoder 500 via a burst address decoder 400. This arrangement provides the "counting method" described above and thereby allows burst mode operation through the main decoder 500.
FIG. 2A is a more detailed circuit diagram of counter 300 shown in FIG. 1. FIG. 2B is a circuit diagram illustrating the generation of the signals for input to carry generators 26 and 40 of FIG. 2A. FIG. 2C is a more detailed circuit diagram of the burst address decoder 400 shown in FIG. 1.
In FIG. 2A, signals ACOB and AC1B are outputs from address buffer 100 and are applied to carry generators 26 and 40 in counter 300. Signals KCOUNT00B and KCOUNT01B are logically formed by the circuit shown in FIG. 2B, and are input into carry generators 26 and 40 in counter 300 in FIG. 2A. In FIG. 2A, signals ADV and ADSCOUNTB are control signals which enable the burst mode. These signals are described in detail, relative to a product designated as part number MCM62486, on pages 7-91 through 7-99 of a 1991 data book entitled "32K.times.9 bit Burst RAM Synchronous Static RAM with Burst Counter and Self-Timed Write" and published by Motorola, which is incorporated by reference herein. Signals KK0 and KK1 are formed by the circuit shown in FIG. 2B, and applied to carry generators 26 and 40 in FIG. 2A.
FIG. 2A is constructed such that a single carry generator generates two counter output signals. The circuits related to an input/output stage of each carry generator 26 and 40 are similar to each other. The outputs of carry generators 26 and 40 are applied to the burst address decoders in FIG. 2C, and the output signals from that burst address decoder circuitry are applied to the main decoder 500 in FIG. 1.
FIG. 3 is an operational timing diagram illustrating the relationship of the primary control signals used in the conventional burst mode of FIGS. 1 and 2. When signal XCONTROL applied to counter control circuit 600 of FIG. 1 goes high, signals ADV and ADSCOUNTB in FIG. 2A also go high. When input signal KCOUNT2B from NOR gates 22 and 36 of FIG. 2A is received, signal XCONTROL increases the output of the counter by one. In operation, carry generators 26 and 40 are reset by a high pulse from signal KCOUNT0. So, whenever signal KCOUNT2B generates a low pulse, signal CA0 alternatingly has the value of 0 or 1 every one cycle to two cycles due to the carry.
As shown in FIG. 1, the output signal of burst address decoder 400 is applied to main decoder 500 via a transmission gate 8 which is controlled by a burst enable signal, KBurstB. Additionally, as shown in FIG. 3, counter 300 is reset when signal KCOUNT0 goes high, and counter 300 is enabled by signal KCOUNT2B, such that the burst enable signal, KBurstB, is low after signal KCOOUNT2B is high. Predetermined data is then applied to main decoder 500 via the transmitting gate 8. Thus, in conventional burst mode operation, as shown in FIG. 3, burst enable signal KBurstB becomes active after a time delay period, shown as "td", after signal KCOUNT0 has been enabled.
The operation of the foregoing circuitry inherently limits the operating speed of the memory device. Thus, it is difficult to perform high-speed operation of the conventional synchronous random access memory device in correspondence with the processing speed of the overall system. Furthermore, the trend towards faster system clocks and larger memory devices exacerbates the problem of conventional synchronous random access memory device operation.